All Digital Fast Locking Pulse Width Control With Programmable Duty Cycle

The aim of all digital fast locking pulse width control circuit is highlighting programmable duty cycle, in this project two delay lines and time to digital convert, in order to get the same accuracy of the first. Now the system can be calculated without look up table, the two stage matrix converter 0f the 0.18-μm CMOS process, The circuit performs well to the input operating frequency ranging for high frequency in MHz, with an input duty cycle of 30% to 70% it achieves programmable output duty cycle range in increments of 6% with 3 bit of data. The use of the D flip flop will reduce Delay line of the circuit. Low jitter noise of the system can be useful in the circuit performance of the system. Duty cycle adjustment is quite helpful in wide variety applications, circuit are quite sensitive to the adverse condition of the atmosphere so to overcome this problem new circuit system has to create the fabrication of the chip with CMOS technology are costly and compact with reducible small chips. The given areas and clock frequency required criteria are calculated with the system.