A Review on Low Power Design and Verification Techniques |
Author(s): |
| Bua Baker , GUJARAT TECHNOLOGICAL UNIVERSITY (GTU) PG SCHOOL, AHMEDABAD |
Keywords: |
| Low Power, Verification, Unified Power Format, Register Transfer Level, Power-Aware |
Abstract |
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In this paper, the fundamental components of low power design and verification are explained in addition to how the UPF (Unified Power Format) with modern techniques facilitates the Power-Aware verification at the RTL, with conventional RTL (Register Transfer Level) design techniques plus reusable blocks. |
Other Details |
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Paper ID: IJSRDV3I41128 Published in: Volume : 3, Issue : 4 Publication Date: 01/07/2015 Page(s): 1944-1947 |
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