Scalable On-Chip Bus and Thread Extension using Open Core Protocol |
Author(s): |
| Manjunath N , UBDT College of Engineering,Davangere,India; Prof. Arun Raj S R, UBDT College of Engineering, Davangere,India |
Keywords: |
| OCP, Soc, OCP Interface, Verilog |
Abstract |
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The technology is getting advanced to the future generation that requires most of the core function an on-chip bus having inter-operability interface irrespective of the core features. The issues that relate to SoC (System on a chip) are 1) a standard communication protocol between different cores. 2) Integration of different clocked domain. 3) The performance increase by system bus. This paper presents the open core protocol (OCP) interface with features such as Basic OCP signals, Simple OCP signals, Burst OCP signals, Tag OCP signals and Thread OCP signals. The Project is optimized with performance, area, power utility, and extended features. These combined improvements enhance the working of a SoC function. The project is designed with Xilinx ISE tool v14.7 in verilog HDL language and verification is done in modelsim. |
Other Details |
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Paper ID: IJSRDV3I41155 Published in: Volume : 3, Issue : 4 Publication Date: 01/07/2015 Page(s): 3179-3187 |
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