FPGA Based Simulation of Clock Gated ALU Architecture with Multiplexed Logic Enable For Low Power Applications

Need of calculation based on hardware systems is increasing day by day. The performance of hardware directly effect the performance of hardware based applications and also the software applications whose execution is affected by hardware performance. So there is continuous need of the improvement in the hardware architectures to achieve a desired level of parametric and interface features. Arithmetic Logic Unit (ALU) is the most busy part of a system. Its performance is directly counted in analyzing the overall system performance. Due to highest activeness of ALU in a system so high performance architecture of an ALU is always desired in a design system. The performance of ALU is, now days, desired to be power efficient to make overall system power efficient and portable. In the presented work a 64-bit architecture of ALU is proposed with gated-clock control logic. The proposed logic design is a low power architecture of ALU. The work is simulated and synthesized using Xilinx ISE Design Tool and the results are tabulated in this paper.