Design of High-Speed VLSI Architecture for LFSR with Maximum Length Feedback Polynomial |
Author(s): |
| Meenal Rambhauji Dadhe , G.H. Raisoni Acadamy Of Engg And Technology; Prof. Anup R Nage, G.H. Raisoni Acadamy Of Engg And Technology |
Keywords: |
| VLSI, LFSR |
Abstract |
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The main purpose of high-speed architecture of linear feedback shift register (LFSR) based on PN Sequence generator technique. PN sequences used for communication purpose cryptography application and for designing encoder, decoder. Depend on the feedback polynomial total number of random sequence generator on LFSR. It is simple counter so its count maximum of 2n-1 by using maximum feedback polynomial. Here in this 8, 32 bit LFSR designed by using VHDL we implement LFSR to study the performance and analysis the behavior of randomness. We also designed purposed architecture which is based on Galois implementation. The analysis is conceded out to find number of gates, memory and speed requirement as the number of bits is increased. We proposed LFSR architecture based on serial, parallel, and also design one application of LFSR ie. BIST for Adder to minimize delay of the system. |
Other Details |
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Paper ID: IJSRDV3I50196 Published in: Volume : 3, Issue : 5 Publication Date: 01/08/2015 Page(s): 283-286 |
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