Implementation of Parallel Multiplier Accumulator Based On Radix-2 Modified Booth Algorithm

This paper presents architecture of multiplier and accumulator (MAC) that is based on modified booth algorithm. The performance of multiplier was improved by combining multiplication with accumulation and using a carry save adder (CSA) tree. The accumulator has the largest delay in the MAC architecture was combined into the CSA then the overall performance was determined. The MAC architecture combines the middle results in the form of sum and carries bits replace of the final adder output, which improves the performance of the multiplier. The multiplier and accumulator architecture radix-2 modified booth algorithm based on spurious power suppression technique (SPST). The booth algorithm decreases the number of partial products rows to half, resulting increase in the speed and performance of the system. Compared to other multiplier, the booth multiplier has the highest operational speed and less hardware count. The SPST technique can decrease the switching power dissipation, which is the significant part of the whole power dissipation in integrated circuits. The proposed MAC can be used in various fields for high performance such as digital signal processing applications.