Performance Comparison of AGFF & DDFF on Johnson Counter

Power reduction is nowadays becoming the first consideration in VLSI design. Low power design is one of major concerns in deeply scaled CMOS technologies. Consequently, the need for power efficient design techniques has grown considerably. Several efficient design techniques have been proposed to reduce both dynamic as well as static power in VLSI circuit applications. Clock gating is one of the most elegant and classic techniques for reduction of dynamic power, major contributor in total power consumption of any VLSI circuit. Since clock signal have been a great source of power dissipation in synchronous circuits because of high frequency and load. So , by using clock gating one can save power by reducing unnecessary switching activity inside the gated module. In this paper two most popular techniques of clock gating are compared for their power saving performance, first is AGFF(Auto-gated FF) based and second is DDFF(Data driven flip flop) based. These designs are implemented using Cadence ADE(Analog design tool) and simulation results shows around 40% power saving using AGFFs and around 25-30% power saving using DDFFs.