VLSI Implementation of Low Power Area Efficient Fir Digital Filter Structures

Filter occupies a major role in digital signal processing. The design of parallel FIR filter structures using Common sub expression elimination technique requires minimum number of multipliers and low power adders. As normally multiplier consume more area and power in comparison of adder. Moreover, along with the increase in length of parallel FIR filter number of adders does not increases. By using common sub expression elimination algorithms, the adopted parallel FIR structures use the basic nature of symmetric coefficients which reduces half the number of multipliers in Sub-Filter section at the amount of additional adders in preprocessing and post processing blocks. In term of silicon area, the weight of multiplier is more than adder so exchanging multipliers with adders is advantageous. Finally the proposed parallel FIR filter structures are superior from existing one in terms of consumption of area and power.