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Efficient Fault Detection and Correction in Memory Application

Author(s):

K.Jayasheeli , Kalaignar Karunanidhi Institute Of Technology; Sajitha.S, Kalaignar Karunanidhi Institute Of Technology; Jensi dhanakiruba.D, Kalaignar Karunanidhi Institute Of Technology; Gokila.S, Kalaignar Karunanidhi Institute Of Technology; Abarna.I, Kalaignar Karunanidhi Institute Of Technology

Keywords:

Single Event Upset, Cyclic Redundancy Check Codes, LDPC, Error Correction Codes

Abstract

The single event upset (SEU), is an unintentional change of state in circuit element of any microelectronic device such as ASICs, and memory application. In this paper, error detection and correction in memory devices using MLDD (majority logic decoder/detector) method with cyclic redundancy check codes (CRC) is introduced. The MLDD is most suitable for memory application due to their large number of error correcting capability. The MLDD detects, whether a word has errors in the first iteration of the decoding, when there are no errors in the decoding end without completing the rest of the iteration. In view of most words in a memory the average decoding time is greatly reduced with error free data. In this paper presents an application of cyclic redundancy check (CRC). The CRC is very effective for error detection in memory devices and digital network. In this technique, this makes the minimal power consumption with quite overhead of memory usage.

Other Details

Paper ID: IJSRDV3I50628
Published in: Volume : 3, Issue : 5
Publication Date: 01/08/2015
Page(s): 1358-1361

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