Fault Coverage Circuit with BIST Architecture for Efficient Hardware Utilization for Testing Applications

Present days, the demand for portable computing devices and communication systems are increasing rapidly. These applications require low power dissipation VLSI circuits. For such circuits power optimization can be achieved by using the new fault coverage Test Pattern Generator (TPG) along with a Linear Feedback Shift Register (LFSR). In order to reduce the testing cost of the chip there are many test parameters that should be improved. These test parameters include: The test power, Test Length (test application time), Test Fault Coverage, Test Hardware Area Overhead. To overcome the issues with external testing Built-in-Self-Test (BIST) is used for testing of the VLSI circuits. BIST performs self testing and reduces the dependence on any external testing equipment. The proposed approach is implemented using a modified conventional LFSR in which transitions are reduced by increasing the correlation between the successive bits. The circuit is tested in the presence of fault and without fault.