Comparative Analysis of Comparators using Different Logic Adder Styles at 180nm

In this paper 4-bit comparators are designed with six different logic of full-adder design styles at 180nm VLSI technology and all designs operated at 3.3Mhz frequency 1.8V that simulates all circuits. The circuits are designed and simulated using Tanner EDA software tools. It is concluded from power dissipation comparison that CMOS has lowest power dissipation results while DVL design style has highest in comparison. It is concluded from Propagation delay comparison that DPL design style has least propagation delay time at 180nm. So it is better to use DPL/DVL logic style to design a system where fast speed is required. The GDI and CPL technique have large delay compare to others. It is concluded from number of transistors comparison that TG technique requires less number of transistor to design a system than other two design styles. So electronics circuits designed using TG logic style will occupy less space on the chip. It is also concluded that TG style has the lowest figure of merit than other two design styles at 180nm. Thus TG and DVL have the best performance in terms of speed and power dissipation at lower supply voltages. It is a also concluded that as technology is scaling down, it is becoming more advantageous in terms of less supply voltages, less power dissipation and having less delay. Main emphasis on Power Delay Product which is less in Transmission gate logic style of adders.