Design and Analysis of 4-Bit Magnitude Comparator of Different Adder Logic Using GDI and TG at 90nm

In this paper 4-bit comparators are designed with six different logic of full-adder design styles at 90nm VLSI technology and all designs operated at 3.3 MHz frequency 1.2V that simulates all circuits. The circuits are designed and simulated using Tanner EDA software tools. It is concluded from number of transistors comparison that Transmission Gate technique requires less number of transistor to design a system than other two design styles. So electronics circuits designed using Transmission Gate logic style will occupy less space on the chip than GDI. It is also concluded that Transmission Gate style has the lowest figure of merit than other two design styles at 90nm. Thus Transmission Gate has the best performance in terms of speed and power dissipation at lower supply voltages. It is a also concluded that as technology is scaling down, it is becoming more advantageous in terms of less supply voltages, less power dissipation and having less delay. Main aim to optimize both power and area of 4-bit magnitude comparator Power Delay Product which is less in Transmission gate logic style of adders.