Comparison of Multiplexer Based Pseudo-Carry Compensation Truncated Multiplier with Standard Multiplier |
Author(s): |
| Sunil M , SHRIDEVI INSTITUTE OF ENGINEERING AND TECHNOLOGY ; Abhilash K G, SHRIDEVI INSTITUTE OF ENGINEERING AND TECHNOLOGY ; Harish B, SHRIDEVI INSTITUTE OF ENGINEERING AND TECHNOLOGY |
Keywords: |
| PCT Truncated Multiplier, FPGA, VLSI Design |
Abstract |
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The conventional multipliers consume more power and area and causes more delay in the system. To overcome these problems, truncated multipliers is applied where it consumes less area, power and delay. But in Truncated multiplier probability of error is more due to truncation of LSP’s, hence compensation circuit need to be added to overcome the probability of error. In this project work Pseudo-carry compensation truncation scheme is implemented where compensation circuit is added to regular truncated multipliers. The proposed PCT multiplier is compared with the conventional multipliers like Braun multipliers, Vedic multipliers, and Booth multiplier and the result is analyzed. The PCT multiplier can be used in the field of Image processing, Digital signal processing Digital communication etc. |
Other Details |
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Paper ID: IJSRDV3I60358 Published in: Volume : 3, Issue : 6 Publication Date: 01/09/2015 Page(s): 857-860 |
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