Comparative Study of CPSFF for Low Power Applications |
Author(s): |
| Surbhi Chaudhary , united group of institutions; Prashant Gupta, ideal institute of technology |
Keywords: |
| Flip Flop, Low Power, Clocked Transistor |
Abstract |
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Power Consumption has a major drawback in VLSI designs. A large part of chip power is consumed by clocking system consists of clock distribution network & flip-flops. The digital systems are required to operate at very low power & needs to be modified for the same. Various techniques are surveyed for this purpose. In this paper, we have use an effective method to reduce capacity of the clock load by minimizing a number of clocked transistors. For this purpose, we use to analyse low power clock paired shared flip flop(CPSFF) for higher performance and design a modified version of CPSFF to further reduce the power consumption by reducing the clocked transistors by using signal feed through (SFT) technique in pull down network. The design has been simulated using Tanner tool with 180nm & 90nm CMOS technology at different voltages for a capacitive load of 15 fF at its output and for no-load condition also. |
Other Details |
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Paper ID: IJSRDV3I70121 Published in: Volume : 3, Issue : 7 Publication Date: 01/10/2015 Page(s): 354-358 |
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