FIR Filter Design for ASIC and FPGA Realization Using DA-Approach

This paper presents approaches for high-throughput with Distributed Arithmetic (DA) based implementation of reconfigurable Finite Impulse Response (FIR) digital filters whose filter coefficients will be changing during runtime. Conventionally, for DA-based implementation of reconfigurable FIR digital filter, the lookup tables (LUTs) are needs to be implemented in RAM, but the RAM based LUT is found to be costly. Therefore, a shared-LUT design is proposed for the realization of DA computation. Instead of using separate registers for storing possible results of partial inner products for DA processing of different bit positions, registers are shared by the DA units for bit slices of different weightage. The proposed design is having nearly less area-delay product, when compared to DA-based conventional structure. The critical operations of the FIR filter are multiplication and accumulation. But Real-time signal processing requires a unit which consumes low power, and having high throughput and high speed Multiplier-Accumulator (FIR) unit, which is always important to achieve a high performance digital signal processing system. To achieve the parallel response of the FIR Filter instead of serial response for the given serial input, DA- Algorithm approach is introduced.