FPGA implementation of modified ADPLL for Dual clock Memory design |
Author(s): |
| Shivprasad.Mallappa.Channangi , BLDEA?s V.P.Dr. P.G.H CET , Vijayapur , KARNATAKA ,INDIA; Mr. Vinay Bagali, BLDEA?s V.P.Dr. P.G.H CET , Vijayapur , KARNATAKA , INDIA |
Keywords: |
| DCO, ADPLL, FPGA, Loop filter, Phase Detector, Dual clock Memory |
Abstract |
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In This Paper, We Propose A Novel Design Of Adpll Which Should Operate In Synchronous With Dual Clock Memory. The Main Blocks Of Adpll Such As Digital Controlled Oscillators Are Implemented With A New Method In Digital Domain For Better Performance. The Digital Controlled Oscillator Is Designed Using Modified Counters Which Reduce The Delay Compared To Traditional Methods. The Increment Decrement Counter Is Modified From Previous Work And Is Designed Using Mux. 200 Hz Is The Central Frequency And Operational Frequency Range Is 997.0089 Hz To 1008.64 Hz Which Is The Lock Range Of The Design. Further The Adpll Is Designed Using Vhdl Language, Synthesized Using Xilinx Ise 14.5 And Implemented Using Xilinx System Generator For Data Serialization Using Spartan 6 Lx45 Fpga Board. |
Other Details |
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Paper ID: IJSRDV3I80153 Published in: Volume : 3, Issue : 8 Publication Date: 01/11/2015 Page(s): 233-236 |
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