Design Approach of High Performance Arithmetic Logic Unit Using Pipelined Multiplier Based on Vedic Mathematics

All of us know that ALU is a module which can perform arithmetic and logic operations. The reason behind choosing this topic as a research work is that, ALU is the key element of digital processors like as microprocessors, microcontrollers, central processing unit etc. Every digital domain based technology depends upon the operations performed by ALU either partially or whole. That’s why it highly required designing high speed ALU, which can enhance the efficiency of those modules which lies upon the operations performed by ALU. The speed of arithmetic is of extreme importance and depends greatly on the speed of multiplier. Therefore the technologies are always looking for new algorithm and hardware so as to implement this operation in much optimized way in the terms of area and speed. Vedic Mathematics deals with various branches of mathematics like arithmetic, algebra, geometry etc in computation algorithm of the coprocessor which will reduce the complexity of execution time, area and power consumption etc. Multiplier based on Vedic Mathematics is one of the fast and low power multiplier. In this paper arithmetic logic unit is design with the pipelining technique based on vedic mathematics to improve the execution speed and consuming power.