Optimizing the Performance of Adders Using Multiplexer and NAND Gates |
Author(s): |
| T.Vanitha , Angel college of engineering and technology; S.Gayathri, Angel college of engineering and technology; S.Baskar, Angel college of engineering and technology |
Keywords: |
| MUX, NAND, FPGA, MICROWIND EDA, Xilinx |
Abstract |
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In This paper provides the performances of adder’s circuit is proposed. The adder circuit is a very familiar method for optimizing speed, surface area. The area, speed is also important parameter to determine the performance of the system. In this paper, the full adder and half adder circuit cells are converting MUX and NAND gates. This type of adders used for design of field programmable gate arrays (FPGA).Simulations can be done by Xilinx 13.1i and layouts for MICROWIND EDA tool with supply voltage 1.8v. |
Other Details |
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Paper ID: IJSRDV3I90201 Published in: Volume : 3, Issue : 9 Publication Date: 01/12/2015 Page(s): 214-217 |
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