Low Power Pulse Triggered Flip Flop using Conditional Pulse Enhancement and Signal Feed through Scheme |
Author(s): |
| Amita , Indus Institute of Engineering and Technology, Kinana, Jind, Haryana - 126102; Sunaina Singroha, Indus Institute of Engineering and Technology, Kinana, Jind, Haryana - 126102 |
Keywords: |
| Flip-Flop, Low power, Pulse Triggered, Signal Feed through Scheme |
Abstract |
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A Low Power Pulse Triggered Flip Flop using Conditional Pulse Enhancement and Signal Feed through Scheme is presented in this paper. Proposed flip flop is used two techniques in combined form with three new modifications. Firstly, clock pulse generator is modified with better pulse enhancement scheme. Second, power supply connection is cutoff during discharging operation. And third, no. of transistors are reduced by removing some unnecessary transistors at intermediate and output nodes. So, proposed flip flop has improved performance in term of power, delay and area. Tanner EDA tool is used in the simulation of 90nm process technology at 500MHz clock frequency. Proposed flip flop has the minimum power delay product than conventional flip flops [3], [4]. |
Other Details |
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Paper ID: IJSRDV3I90385 Published in: Volume : 3, Issue : 9 Publication Date: 01/12/2015 Page(s): 526-528 |
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