Minimum Energy tracking for digital arithmetic and logical units

In modern world there is a need for low power digital end design and area efficient low power, high performance in Digital signal Processing system. Power minimization is one of the important factors in today VLSI design methodologies because of two main reasons one is the operating life of the battery in portable devices and mobiles. The second reason is due to the increasing number of transistors on a single chip results in high power dissipation and it can lead to reliability. Recent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI digital signal processing (DSP) systems. One of the most widely used operations in DSP is finite-impulse response (FIR) filtering. In the integrated circuit design the packaging problems is a major element to minimize the energy consumption in system. Hence it is important to track the system continuously with respect to time, the minimum operating voltage of digital circuits which in turn depends upon the systems working logics with conventional and logical design. In this regard, as a preliminary work 32 Tap FIR filter that includes adder, multiplier and a D flip flop as a delay element was designed and tested with the parameters such as delay, power and number of flip flops. The FIR filters were implemented using 8 bit input word length and 8-bit coded coefficients. This design presents the conventional 32 Tap Finite Impulse Response filter and it is synthesized in Xilinx design tool.