Pulse Triggered Pass Transistor based Power Efficient Flip Flop |
Author(s): |
| Preeti Kumari , CDAC Noida; Dr. Arti Noor, H.O.D, S.O.E. CDAC |
Keywords: |
| TG, Pass Transistor, P.D.P, Low Power |
Abstract |
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In this paper, a pass-transistor based low power pulse triggered flip-flop design is conferred. In this configuration, the clock pulse is generated with two input AND gate circuitry for reducing the discharging path improve the speed, and reduce the circuit complexity. In the proposed design the architecture is simplified by removing the feedback along with pseudo NMOS. As compared to the self-driven pulse triggered flip-flop, the proposed pulse triggered flip-flop design features are best power, minimum delay and Power-Delay-Product (PDP) performance along with minimum number of transistors. This is designed and simulated in Xmanager 4 with 3.5 V supply voltage and 350 Nanometer technologies. |
Other Details |
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Paper ID: IJSRDV4I100118 Published in: Volume : 4, Issue : 10 Publication Date: 01/01/2017 Page(s): 224-226 |
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