Performance Evaluation and Design of Low Voltage Low Power Lector Inverter Based Two Fold Comparator |
Author(s): |
| Surendra Kumar , APEX INSTITUTE OF ENGINEERING AND TECHNOLOGY JAIPUR; Vimal Agarwal, APEX INSTITUTE OF ENGINEERING AND TECHNOLOGY JAIPUR |
Keywords: |
| Double-Tail Comparator, Dynamic Clocked Comparator, High-Speed Analog-To-Digital Converters (ADCS), Low-Power Analog Design |
Abstract |
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Another blueprint of comparator which is essential bit of ADC is proposed. In this paper new arrangement of twofold tail comparator with bleeding edge arrangement of regenerative inverter is available. Proposed inverter gives less power disseminating less delay than customary inverter. New proposed arrange gives 25% reduction in power diminishment and 75% decreasing in kickback noise which is most fundamental parameter of comparator. The new layout is reproduced in TSMC180nm in Tanner gadget which are measured to choose control scrambling, speed and kickback commotion. These are differentiated and past frameworks. |
Other Details |
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Paper ID: IJSRDV4I120515 Published in: Volume : 4, Issue : 12 Publication Date: 01/03/2017 Page(s): 521-523 |
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