Low Power Low Area Shift and Add Multiplier Architechure Using BZ-FAD

The Digital Signal Processing (DSP) is one of the core technologies in multimedia and communication systems. Most of DSP applications such as fast Fourier transform (FFT) require additions and multiplications. A digital multiplier is the fundamental component in general-purpose microprocessors and in digital signal processors. In this paper very low power multipliers is proposed which uses shift and add architecture for its operation. Here we are trying to reduce the switching activity of the circuit. We are going to implement the circuit using a low power delay buffer which uses ring counter designed with clock gated by C-element[1]. In digital VLSI system the clock distribution network and flip-flops are most power consuming components. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating clock frequency by half, which considerably reduces the power consumption. The c-element can avoid the possibility of glitches, a crucial property for a clock gating signal. The ring counter with clock gated by the C-elements can effectively eliminate the excessive data transition without increasing loading on the global clock signal. The proposed architecture also uses BZ- FAD technology, hence reduces the switching activity. The proposed architecture not only lowers the switching activity but also reduces the unwanted data transmission and power consumption.