Approximate Mode of Wallace Tree Multiplier using Adiabatic Logic on Fin-FET for Video-Encoding

Approximate computing has been gaining momentum over the past few years with progressive research particularly in applications exercising signal processing techniques. Human imperceptibility could be taken advantage of by some image and video compression standards such as JPEG and MPEG which have tolerance to computing imprecisions that yields an algorithm possessing power efficiency. With hardware approximations that are often statistically fixed, the prevailing architectures are not very efficient in adapting to different inputs, like in the case of MPEG coder whose output quality varies significantly for different input videos due to their fixed approximation hardware configurations. This paper faces the above mentioned issue by proposing a reconfigurable approximate architecture for MPEG encoders. This is achieved by designing arithmetic unit using Adiabatic Vedic alias low power high speed technique that with a FinFET device. Further, low area overhead helps in solving the issues prevalent in conventional design, like power variant, and speed up-gradation, area consumption. Low power and high speed CLA have to be designed using adiabatic Vedic gates (EEAL), followed by the Arithmetic unit (Multiplier) which must be implemented using the Proposed Adiabatic Vedic CLA. The overall architecture has sufficient energy, power consumption reduced delay architecture and saves area which enhances its utility value.