Implementation of Single Precision Floating Point Multiplier on FPGA |
Author(s): |
| Mamatha M , KALPATARU INSTITUTE OF TECHNOLOGY,TIPTUR; S Pramod Kumar, KALPATARU INSTITUTE OF TECHNOLOGY,TIPTUR |
Keywords: |
| Floating Point; Multiplication; FPGA |
Abstract |
|
In this paper we depict an effective usage of an IEEE 754 single precision floating point multiplier focused for Xilinx Spartan 3E FPGA. Verilog HDL is utilized to actualize an innovation. The multiplier execution handles the overflow and underflow cases. Adjusting is not actualized to give more accuracy when utilizing the multiplier as a part of a Multiply and Accumulate (MAC) unit. The multiplier was confirmed against Xilinx floating point multiplier center produced by Xilinx coregent. |
Other Details |
|
Paper ID: IJSRDV4I21334 Published in: Volume : 4, Issue : 2 Publication Date: 01/05/2016 Page(s): 1598-1602 |
Article Preview |
|
|
|
|
