Low Power UART Design using Low Power Techniques |
Author(s): |
| Christine Qureshi , Inderprastha Engineering College, AKTU; Amita Agnihotri, Inderprastha Engineering College, AKTU |
Keywords: |
| UART, Vivado, clock gating, Baud rate |
Abstract |
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With UART, serial communication can be implemented between remote embedded systems and peripherals. Based on fixed frequencies with a sampling method the UART protocol is used to achieve robustness under reasonable frequency variations between systems for cheap and low speed applications. This work investigates whether low power techniques like clock gating can be advantageously implemented in a UART receiver for clock power reduction. The proposed clock gating technique reduces unnecessary clock transitions of functional blocks in IDLE state and also dynamic power in running state not affect the design functionally |
Other Details |
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Paper ID: IJSRDV4I21646 Published in: Volume : 4, Issue : 2 Publication Date: 01/05/2016 Page(s): 1763-1765 |
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