Enhanced Key Expansion Algorithm of AES for encryption using FPGA Implementation |
Author(s): |
| Amrutha T V , KALPATARU INSTITUTE OF TECHNOLOGY,TIPTUR; N R Prashanth, KALPATARU INSTITUTE OF TECHNOLOGY,TIPTUR |
Keywords: |
| Advanced Encryption Standard; FPGA; Key expansion; Sub word; Rot word; Rconst |
Abstract |
|
The primary point of this paper is scramble the information utilizing Advanced Encryption Standard (AES) calculation. In AES calculation cryptography procedure is utilized. Security is most critical in information correspondence so to build the security key development calculation is utilized .In this paper we attempted to lessen the region and the LUTs. To diminish LUTs here considering the relative change strategy is utilized. The round key development is proposed to enhance security against assaults. Scrambled information utilizing AES calculation technique .In AES calculation quantities of round performed amid execution will be relied on the Key length. Here AES - 128 bits key are utilized, so number of round performed amid execution will be 10. This calculation is reproduced utilizing Xilinx programming and executed on FPGA. |
Other Details |
|
Paper ID: IJSRDV4I21657 Published in: Volume : 4, Issue : 2 Publication Date: 01/05/2016 Page(s): 2025-2028 |
Article Preview |
|
|
|
|
