Design and Implementation of Analog CMOS Phase Locked Loop using 180nm technology |
Author(s): |
| Komal Kadikar , Sankalchand Patel College of Engineering, Visnagar; Dr. Kehul A. Shah, Sankalchand Patel College of Engineering, Visnagar |
Keywords: |
| Locking time, phase & frequency detector (PFD), charge pump(CP), voltage controlled oscillator(VCO), frequency divider(FDIV), phase locked loop(PLL), power consumption |
Abstract |
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This paper deals with the design of Phase Locked Loop for achieving faster locking loop. The specific quality and property of fast locking of PLL is required in many clock and data recovery circuits. Many researches have been made to reduce this locking time but at the expense of power, phase noise and other parameters. Here, a PLL is implemented with redesigning of individual blocks like, phase and frequency detector(PFD) is designed using D flip flop to reduce area and static phase error, charge pump(CP) is designed to reduce the current mismatch using current mirrored structure and VCO has been designed using five stage current starved voltage controlled oscillator. The PLL is designed using 180 nm CMOS technology with 1.8 V power supply voltage. |
Other Details |
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Paper ID: IJSRDV4I21690 Published in: Volume : 4, Issue : 2 Publication Date: 01/05/2016 Page(s): 1992-1995 |
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