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Design And Implementation Of Sobel Edge Detection On FPGA Using Noc Concepts

Author(s):

Neha Goyal , Vishwakarma Government Engineering College, Chandkheda Ahmedabad; Prof. N. P. Patel, Vishwakarma Government Engineering College, Chandkheda Ahmedabad

Keywords:

Edge detection Enhancement Algorithm, NoC, FPGA, Real time, Parallel Processing, Kintex-7

Abstract

In today’s world fast computing is required to handle large amounts of data. Real time image processing and video processing requires billions of computations per second which is impossible to do with sequential algorithm. To speed the processing of the tasks up, we need to design hardware that can harness parallel nature of the application to be run. Multimedia, scientific and engineering applications have large amount of data and hence require fast computing. Thus parallel computing architectures are becoming a necessity due to increasing computational demands by these applications. In this work, we implement Sobel edge detection algorithm on multiple cores on Xilinx Kintex 7 FPGA. Our NoC based design allows parallel execution of the algorithm unlike the sequential execution done by a single core. The system was designed in Verilog and Synthesized on Kintex-7 FPGA. The multiple cores in our implementation are connected over a NoC-based architecture which accelerates the speed of image processing by 41% as compared to a sequential FPGA implementation.

Other Details

Paper ID: IJSRDV4I21746
Published in: Volume : 4, Issue : 2
Publication Date: 01/05/2016
Page(s): 1514-1519

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