Design of 16 X 16 Vedic Multiplier |
Author(s): |
| PATEL NIRAJ GULABBHAI , VISHWAKARMA GOVERNMENT ENGINEERING COLLEGE, CHANDKHEDA; ALPESH PATEL, VISHWAKARMA GOVERNMENT ENGINEERING COLLEGE, CHANDKHEDA |
Keywords: |
| Vedic Mathematics, Vedic Multiplier, Array Multiplier, Urdhva - Triyagbhyam Sutra |
Abstract |
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Design of Multiplier unit using Vedic Mathematics. Urdhva-Tiryagbhyam (vertically & crosswise) algorithm is the one of the multiplication technique. To reduce the partial product and to improve speed we have used this algorithm. Also different types of adders to reduce the partial product addition. Here design of 16X16 Vedic Multiplier using different adders and comparison of their delays. These delays compared to search for the best architecture. Design of the same implemented on XILINX ISE-14.5 simulator, Spartan-3 family and design coding in Verilog- HDL. |
Other Details |
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Paper ID: IJSRDV4I21772 Published in: Volume : 4, Issue : 2 Publication Date: 01/05/2016 Page(s): 1508-1510 |
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