An Approach for Implementation of Bus Arbitration Techniques

In modern days, due to down scaling in technologies have led to highly complex billion transistor integrated circuits (ICs).As a consequence, manufacturers are integrating increasing number of components on a chip. A heterogeneous System on Chip (SoC) might include one or more programmable components such as general purpose processor cores, digital signal processor cores, or application specific intellectual property cores (IPs) as well as an analog front end, On-chip memory, I/O devices and other application specific components. In SoC, multiple IPs need to communicate with each other to access the required functionality. When multiple IPs requests the bus at the same time, contention may occur. This makes on-chip bus based communication a major challenge for the system designer in the current SoC technology. Thus, Bus arbiters are proposed. The masters on a SoC bus may requests simultaneously and hence an arbiter is required to decide which master is granted. To do so different algorithms are developed. In this paper an approach for implementation of bus arbitration techniques like RR, FCFS and Token Pass are discussed.