An Enhanced Image Cryptographic Method Based On AES Rijndael Algorithm |
Author(s): |
| Sindhu G R , VVIET, Mysuru; Anitha D B, VVIET, Mysuru |
Keywords: |
| AES, Rijndael, Block cipher, Encryption, Decryption, FPGA, VHDL |
Abstract |
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Now a day’s a lot of internet and wireless connections customers has led to an enhancing need for solutions of security measures and devices for protecting the consumer details approved on over the unsecured network so that unlawful people cannot access it. As we share the important details through wireless media it should provide details comfort, stability and entity confirmation. The symmetric block cipher works a big part in the bulk details protection. Advanced Encryption Standard (AES) as Rijndael algorithm provides data protection. AES has the key advantages of being used in both software and hardware. Hardware implementation of the AES has a lot of benefits such has prolonged throughput and better protection level. The design uses an iterative looping approach with block 128 bits and key size of 128 bits, 192 bits and 256 bits, the lookup table implementation of S-box so as to reach the purpose of improving the system computing speed the pipe-lining and parallel processing methods were used. Components Performance for 128 bit AES (Advanced Security Standard) protection and decryption has been made using VHDL. The recommended requirements for encryption and decryption aspect will functionally verified using modelsim, will be synthesized using Xilinx_ISE_13.2 software Spartan-3 FPGA platform and assess the design for the power, throughput & area. |
Other Details |
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Paper ID: IJSRDV4I30827 Published in: Volume : 4, Issue : 3 Publication Date: 01/06/2016 Page(s): 1247-1251 |
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