An Efficient Error Correction Code for A Smart Reliable Network-On-Chip

Networks on Chip plays a vital role in development of VLSI design and it is one of the solutions for faster on chip communication. In this paper a new network-on-chip is proposed that handles accurate localizations of the faulty parts of the NoC. The proposed NoC handles new error detection mechanisms suitable for dynamic NoCs, and the errors are detected and corrected efficiently in order to have a fault free data transmission. The presented mechanisms are able to distinguish permanent and transient errors and localize accurately the position of the faulty blocks such as data bus, input port, output port in the NoC routers, while preserving the throughput, the network load, and the data packet latency. The proposed method uses Decimal Matrix Code concept which utilizes decimal algorithm to obtain the maximum error detection capability. The proposed DMC is compared to the existing Hamming code which corrects only one bit error, whereas DMC can correct up to 16 bits error. As a result this improves the error correction capability and enhances data reliability.