Design of Binary and BCD Adders Using Reversible-Logic Gates

Reversible logic is emerging as one, low cost substitution for the existing methods with respect to its speed, less power consumption and area. Adder design is a very fundamental and important part of any processor and optimal design of such adders gives efficient output in the form of better working processors. We are proposing a better Binary and BCD adders. The designs of these adders are cored to optimize total cost, delay in processing and area occupied. A modification we are proposing in BCD adder stages to remove the redundant part present in the circuit allowing the design to work more efficiently. We would explore the utilization of negative control lines for detection in overflow logic of BCD adder which significantly cuts off total cost, time delay and counts of individual gates, outcome of such utilization is high speed BCD adder with optimum area. This results in vast possibilities in the field of reversible computing.