Low Power Full-Adder Design with Gate-Diffusion-Input MUX |
Author(s): |
| SANGAMESH NANDEPPANAVAR , BLDE A's Dr. P.G. HALAKATTI COLLEGE OF ENGG & TECH, VIJAYPUR; Mr. V.A. BAGALI, BLDE A's Dr. P.G. HALAKATTI COLLEGE OF ENGG & TECH, VIJAYPUR |
Keywords: |
| Gate-Diffusion-Input MUX, Full-Adder Design |
Abstract |
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This paper proposes a new method for implementing a low-power full-adder-circuit by means of a set of Gate-Diffusion-Input cell based-multiplexers. Full-adder is a very important part of all digital-circuits and it can be used in variety of Application-Specific-Integrated-Circuits (A-S-I-Cs). If the energy usage of a circuit in VLSI chip is very less, it’ll be most important aspect for the designer. Here the technique used to realize the FA uses less energy and works faster than conventional one. The simulation readings and outputs using a simulation tool illustrate the outputs that can be compared with the conventional CMOS FA. Energy usage, speed-of-circuit and area-on-silicon, comparison between conventional and proposed full adder is also illustrated. |
Other Details |
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Paper ID: IJSRDV4I31230 Published in: Volume : 4, Issue : 3 Publication Date: 01/06/2016 Page(s): 1327-13360 |
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