Design and Analysis of a High Performance-Low Power Conditional Discharge Flip Flop using 90 nm CMOS Technology |
Author(s): |
| Sonam Parihar , BTKIT Dwarahat; Rachana Arya, BTKIT Dwarahat |
Keywords: |
| CMOS circuits, low power, flip-flops, power consumption |
Abstract |
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Low power flip-flops are crucial for the design of low-power digital systems. In this paper, a novel low-power high performance pulse-triggered flip-flop using Modified (proposed) conditional discharging flip-flop (MCDFF) circuit is presented. It is based on the conditional discharging technology. The modified design reduces the number of transistor and achieves better speed and power performance other flip flop (ep-CDO, CDFF, SCDFF, MHLFF). All the simulation results, based on 90-nm CMOS technology, reveal that the proposed design features the best power-delay-product performance. Here, a comparison of existing Flip-Flop (FF) system with different parameters is presented. |
Other Details |
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Paper ID: IJSRDV4I40235 Published in: Volume : 4, Issue : 4 Publication Date: 01/07/2016 Page(s): 213-216 |
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