Optimizing Area and Power of Shift-Register using SSA-SPL Technique |
Author(s): |
| Manjunath Wathar , BLDEA'S DR.P.G.HALAKATTI CET VIJAYAPUR-03; Mr. V. A. Bagali, BLDEA'S DR.P.G.HALAKATTI CET VIJAYAPUR-03 |
Keywords: |
| Pulsed latch, flip-flop, Pulsed-Clock, Shift-registers |
Abstract |
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In this paper we will study that how to reduce area and power of a “Shift-register using Pulsed- Latches.†The size and energy utilization are lessened by superseding F-F with pulsed-latches. This strategy solves the timing-problem between pulsed-latches through the use of multiple non-overlap delayed pulsed-clock signals instead of the conventional single pulsed-clock signal. The shift-register uses a less few pulsed-clock signals by gathering the latches to a few sub-shifter Registers with temporary storage latches. A 128-bit shift-register using pulsed-latches was made using a 0.18μm C-M-O-S process. The energy utilization is 1.2-mW at a 100-MHz clock-frequency. The proposed shift-register reduces 37 % size and 44 % energy with ordinary shift-register with Flip-Flop. |
Other Details |
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Paper ID: IJSRDV4I40329 Published in: Volume : 4, Issue : 4 Publication Date: 01/07/2016 Page(s): 310-314 |
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