A Low Power Design of Redundant Binary Multiplier using Parallel Prefix Adder |
Author(s): |
| R. Maria Baby , FRANCIS XAVIER ENGINEERING COLLEGE, TIRUNELVELI; L. R. Priya, FRANCIS XAVIER ENGINEERING COLLEGE |
Keywords: |
| modified booth encoding, partial product row, error correcting word |
Abstract |
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A redundant binary (RB) representation is used for designing high performance multiplier. Because of its high modularity and carry free addition. The error correcting word (ECW) plays an important role in redundant binary multiplier. The redundant binary (RB) coding and modified booth (MB) encoding creates the error correcting word. The extra error correcting is eliminated by combining the error correcting word into partial product (PP) row. Therefore it saves RBPP accumulation stage. In conventional method, the final addition is carried out by carry select adder (CSA). In the proposed method the parallel prefix adder used. The simulation result shows the significant improvement in area and power when compared with existing RB multiplier. |
Other Details |
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Paper ID: IJSRDV4I40406 Published in: Volume : 4, Issue : 4 Publication Date: 01/07/2016 Page(s): 302-305 |
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