A Verilog Prototype for Scalable Binary Detector |
Author(s): |
| A L Siridhara , MLRIT; D. Chandrababu, MLRIT |
Keywords: |
| FPGA, Xilinx, ModelSim |
Abstract |
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In this paper a prototype was developed in regard of verilog for overall binary demodulator by considering input chips as the feeder. The prototype developed looks for a prescribed format of chipping signal. When the desired sequence of chip is found the prototype is locked by releasing first output. The algorithm and coding pertaing to this is done and simulated through ModelSim Simulator and is implemented on Xilinx Virtex FPGA device. |
Other Details |
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Paper ID: IJSRDV4I40460 Published in: Volume : 4, Issue : 4 Publication Date: 01/07/2016 Page(s): 600-602 |
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