Design of Partially Parallel Polar Encoder Architecture using Verilog |
Author(s): |
| A.BALAJI , PATHFINDER ENGINEERING COLLEGE(PECH), ; A.BALAJI, PATHFINDER ENGINEERING COLLEG(PECH), ; M.SRUJANA , PATHFINDER ENGINEERING COLLEG(PECH) |
Keywords: |
| ECC, Encoding, Parallel Processing, Butterfly Architecture |
Abstract |
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The polar writing was one among the most effective error correcting code attributable to the channel achieving property. The prevailing parallel encoder was additionally higher and simple to implement however it's not applicable for long polar codes as a result of it needed Brobdingnagian space quality. During this paper it consist a main purpose of encryption method with terribly giant scale integration it proposes a re-placement encryption style which might applicable for long polar codes. because the projected polar encoder will applicable for any style and any polar code with high performance and fewer hardware quality. |
Other Details |
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Paper ID: IJSRDV4I40842 Published in: Volume : 4, Issue : 4 Publication Date: 01/07/2016 Page(s): 1018-1022 |
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