Efficient FPGA Realisation of Da-Based Fir Digital Filter for Power and Area Optimization |
Author(s): |
| Mayuri Purushottam Chaudhari , Priyadarshini college of engineering,NAgpur; Dr. S. S. Shriramwar, Priyadarshini college of engineering nagpur |
Keywords: |
| FPGA, DA (Distributed Arithmetic), FIR, LUT |
Abstract |
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The paper presents the details of the realisation of FIR filter using distributed arithmetic technique exploiting the look up tables in FPGA. In this project the reconfigurable filter is implemented and tested using audio codec FPGA. To check the filter operations a noise contained music is played through a microphone and ADC will convert this analog signal to the digital one to be processed in filter using FPGA. After processing in filter signal will be given to DAC will convert it into analog signal to be heard from the Line_out port. Instead of ROM we have used DRAM here for variable coefficients. The filter is tested by the microphone and speaker. |
Other Details |
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Paper ID: IJSRDV4I50104 Published in: Volume : 4, Issue : 5 Publication Date: 01/08/2016 Page(s): 204-206 |
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