Design and Implementation of Multiply Accumulate Unit For Large Arith-Metic Unit Operations |
Author(s): |
| M. Saipriya Sharanya , JYOTHISHMATHI INSTITUTE OF TECHNOLOGICAL SCIENCES; Venu Adepu, JYOTHISHMATHI INSTITUTE OF TECHNOLOGICAL SCIENCES |
Keywords: |
| Digital Signal Processing, ALU, Wallace Tree, carry save adder, Accumulator |
Abstract |
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The proposed paper consisting the design and implementation of the 64 bit MAC (Multiply Accumulate Unit) for large number of arithmetic operations. The proposed design has multiplier and accumulator units, multiplier block perform normal multiplication operation. The proposed multiplication can be designed by using Wallace tree algorithm. And accumulator it performs two operations; one is storing and another one addition of products. The proposed MAC technique can be used in several ALUs and many types of Digital Signal Processing apllications. The proposed design was implemented with Verilog HDL and simulated by XILINX ISE 14.5 synthesis tool. |
Other Details |
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Paper ID: IJSRDV4I50628 Published in: Volume : 4, Issue : 5 Publication Date: 01/08/2016 Page(s): 1105-1108 |
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