Design and Analysis of Adaptive Hold Logic based Aging-AWARE Reliable Multiplier using Variable Latency

Digital multipliers are along with the majority critical arithmetic functional units. The general performance of the Digital multiplier systems depends on throughput of the multiplier. The negative bias temperature instability effect occurs when a pMOS transistor is under negative bias (Vgs = −Vdd), increasing the threshold voltage of a pMOS transistor and falling the multiplier speed. In the same way, positive bias temperature instability occurs when an nMOS transistor is under positive bias. Both effects degrade the speed of the transistor and in the long term, the system may be fail due to timing violations. For that reason, it is required to design reliable high-performance multipliers. In this paper, we implement an aging-aware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier is able to provide the higher throughput through the variable latency and can adjust the adaptive hold logic (AHL) circuit to lessen performance degradation that is due to the aging effect. The proposed design can be applied to the column bypass multiplier. Additionally, the proposed design can be applied to a column- or row-bypassing multiplier. The experimental results show that our proposed design with 16bit and 32bit, 64bit column-bypassing multipliers.