An Improved Fused Floating Point Three Term Adder

Floating Point addition and subtraction units are widely used in various digital and signal processing applications. A traditional Floating Point Three Term Adder performs two additions using discreet units. To perform two additions in a single unit, architecture must be fused so that two adder units work as a single unit. In fused floating point adder, several optimization techniques are applied in order to further enhance the results like exponent compare and alignment unit, dual reduction, leading zero anticipator etc. In the proposed approach, fused floating point adder is implemented with each of the units and optimization techniques working in parallel, so as to reduce the delay in computation. Besides the pipelined approach, Carry Select Adder which is the fastest adder in the literature and is a combination of two ripple carry adders is used in the addition for the further enhancement in timing performance of the unit. Results also show that the timing is improved by reasonable value with the combined implementation of carry select adder and pipelined approach.