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A Review Paper on Reconfigurable Techniques to Improve Critical Parameters of SRAM

Author(s):

Yogit P Palan , Noble Group of Institution, Bhesan Road, Via Vadal, Nr Bamangam, Junagadh, Gujarat, India,; Sangani Vivekkumar D, Dr.Subhash Techincal Campus,Junagadh; Kalpesh Chheladiya, Dr.Subhash Techincal Campus,Junagadh; Divyang Shah, Noble Group of Institution, Bhesan Road, Via Vadal, Nr Bamangam, Junagadh, Gujarat, India,

Keywords:

SRAM, dynamic power, read/write delay, area, leackage parameters

Abstract

Very Large Scale Integration (VLSI) is the process of manufacturing an integrated circuit (IC) by combining thousands of transistor into a single chip for the production of processors, memories and various application specific ICs. In the world of Electronics Technology, memory devices have always played a noteworthy role in technical advancement. In recent years, the demand of SRAM memory in portable devices and high speed processors has increased significantly. Static means it needs not to be refreshed periodically unlike DRAM. This feature makes SRAM significantly faster than DRAM. In this review paper, different SRAM cell variants are compared and reviewed based on simulation results of various critical parameters like power, dynamic power, delay, area and read/write delay, lower bit line capacitance, reduced metal complexity and notch-less design. These parametric comparisons are dynamically shown for 4T, 6T, 7T, 10T configurations of SRAM cells by using 65, 45 & 32 nm CMOS technologies.

Other Details

Paper ID: IJSRDV4I90319
Published in: Volume : 4, Issue : 9
Publication Date: 01/12/2016
Page(s): 525-529

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