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Faster Approach to Image Processing using Vedic Mathematics


RanjanaKumari , DPCOE Pune, India ; Monali Chinchamalatpure, DPCOE Pune, India


DCT, MATLAB, Vedic Mathematics, FPGA, Xilinx


This review paper Faster Approach to Image Processing using Vedic Mathematics. Multipliers are fundamental and area intensive component in the architecture of any DSP system. In many areas, there are situations where the complexity and delay of the whole circuit increases because of inefficient multipliers. So it is necessary to reduce such complexity of Multipliers for efficient DSP architecture with high throughput and time consuming. The algorithm is implemented using verilog HDL and is tested and verified with MATLAB also. The multiplier can be substituted for conventional multipliers in various applications. The exploration of Vedic algorithms in Digital Signal Processing prove to be extremely advantageous. Hence it can be applied for discrete cosine transform application.

Other Details

Paper ID: IJSRDV5I10006
Published in: Volume : 5, Issue : 1
Publication Date: 01/04/2017
Page(s): 55-57

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