An Efficient Design of Reconfigurable Reversible Gate for Data Encryption and Decryption

The development in the field of nanometer technology leads to minimize the power consumption of logic circuits. Reversible logic design has been one of the promising technologies gaining greater interest due to less dissipation of heat and low power consumption. On the other hand, reversible logic circuits can decrease energy dissipation theoretically to zero. Recently an approach to encryption/decryption based on using reversible logic circuits has been proposed. This paper presents a solution to designing encryption and decryption schemes based entirely on reversible logic. In our solution a building block of an encryption and decryption scheme is a cascade of 4-input reversible gates. In this way the building block can perform any reversible 4-variable function. For this purpose a reconfigurable reversible gate has been proposed. The design of such a reconfigurable gate built from standard reversible gates, i.e. NOT, CNOT, Toffoli and Fredkin gates, is presented. In the paper a complete scheme for encryption/decryption of 9-bit data is described using Verilog HDL language and its quantum cost is calculated. Simulation and verification of this scheme is presented on Xilinx ISE 14.7.