BIST Enabled UART using VHDL |
Author(s): |
| R Jamuna , SNS College of Engineering; N Manisha, SNS COLLEGE OF ENGINEERING; R Ragavi, SNS COLLEGE OF ENGINEERING; M Nivetha, SNS COLLEGE OF ENGINEERING; M Preethi, SNS COLLEGE OF ENGINEERING |
Keywords: |
| Built-In-Self-Test (BIST), Universal Asynchronous, Receive Transmit (UART) |
Abstract |
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Asynchronous serial communication is usually implemented by Universal Asynchronous Receiver Transmitter (UART), mostly used for low expense, low speed, short distance data transmission between processor and peripherals. UART is capable full duplex serial communication link, and it has been used in data communication and control system. Also, design systems without full testability are about to the increased possibility of product failures and missed market opportunities. BIST is a testing technique that allows a circuit to test automatically itself. In this paper, the simulation result performance achieved by BIST enabled UART architecture through VHDL programming has been implemented. This technique generate random test pattern automatically, so it can provide less test time compared to an externally applied test pattern and helps to achieve much more productivity at the end. |
Other Details |
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Paper ID: IJSRDV5I10751 Published in: Volume : 5, Issue : 1 Publication Date: 01/04/2017 Page(s): 1409-1410 |
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