Design and Performance Analysis of CMOS full adder Circuits |
Author(s): |
| Saroj Kumari , Guru Jambheshwar University of Science & Technology, Hisar |
Keywords: |
| full adder, low power, temperature, technology |
Abstract |
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We present two designs of full adder in this paper; one is 28t conventional design full adder and another is 16t PTL design full adder. These designs are implemented on two technologies 90 nm and 180 nm using mentor graphics. Power consumption is calculated on various supply voltages and temperatures. Results are prepared and compared with other research papers and our results for 16t full adder are found satisfactory. |
Other Details |
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Paper ID: IJSRDV5I10844 Published in: Volume : 5, Issue : 1 Publication Date: 01/04/2017 Page(s): 1249-1252 |
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