A Survey On High speed And Low Power Consumption CMOS Phase-LockedLoop |
Author(s): |
| Ankita Choudhary , BMCT, Indore (M.P.); Ankita Choudhary, B.M. College of Technology & Science, Indore, (M.P.) |
Keywords: |
| CMOS, Phase-locked loop (PLL) |
Abstract |
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In recent years, there has been a significant research effort in the area of high-speed electronics for communication and signal processing. High speeds are required in order to take full advantage of the extremely broadband capabilities of optical fibers. At the same time, the old communication protocols that use different low speeds are still being widely used. In order to be flexible for the different protocols, a large locking range PLL clock generator is highly needed. Phase-locked loop (PLL) which constitutes a basic building block for many synchronizers like carrier recovery or timing recovery is essential in most digital communication systems. The phase locked loop system are very important unit of the system. This paper discusses the study of the different types of CMOS phase locked loop. |
Other Details |
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Paper ID: IJSRDV5I110305 Published in: Volume : 5, Issue : 11 Publication Date: 01/02/2018 Page(s): 512-514 |
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